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NB6L16 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/Translator Buffer
The NB6L16 is a high precision, low power ECL differential clock or data receiver/driver/translator buffer. The device is functionally equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With output transition times of 70 ps, it is ideally suited for high frequency, low power systems. The device is targeted for Backplane buffering, GbE clock/data distribution, Fibre Channel distribution and SONET clock/data distribution applications. Input accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV ECL signals. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
Features http://onsemi.com MARKING DIAGRAMS*
8 1 SOIC-8 D SUFFIX CASE 751 1 8 6L16 ALYW G
8 1 TSSOP-8 DT SUFFIX CASE 948R A L Y W G
8 6L16 ALYWG G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
* * * * * * * * * * *
Maximum Input Clock Frequency w 6 GHz Typical Maximum Input Data Rate Frequency w 6 Gb/s Typical Low 12 mA Typical Power Supply Current 70 ps Typical Rise/Fall Times 130 ps Input Propagation Delay On-Chip Reference for ECL Single-Ended Input - VBB Output PECL Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V Open Input Default State LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input Compatible Pb-Free Packages are Available
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
1
March, 2007 - Rev. 6
Publication Order Number: NB6L16/D
NB6L16
VCC
NC
1
8
R2 D 2 R1 R1 R2 7 Q
D
3
6
Q
VBB
4
5
VEE
Figure 1. Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin 1 2 Name NC D I/O - LVDS, CML, LVPECL, LVNECL, LVTTL, LVCMOS Input LVDS, CML, LVPECL, LVNECL, LVTTL, LVCMOS Input - - ECL Output ECL Output - - Default State - LOW Description No Connect. The NC pin is electrically connected to the die and MUST be left open. Non-inverted differential clock/data input. Internal 75 kW to VCC and 37.5 kW to VEE. Inverted differential clock/data input. Internal 37.5 kW to VCC and 75 kW to VEE. Internally generated ECL reference voltage supply. Negative power supply voltage. Inverted differential ECL output. Typically terminated with 50 W resistor to VCC - 2.0 V. Non-inverted differential ECL output. Typically terminated with 50 W resistor to VCC - 2.0 V. Positive power supply voltage.
3
D
HIGH
4 5 6 7 8
VBB VEE Q Q VCC
- -
Table 2. ATTRIBUTES
Characteristics Internal Input Default State Resistor Internal Input Default State Resistor ESD Protection (R1) (R2) Human Body Model Machine Model Charged Device Model Value 37.5 kW 75 kW > 2 kV > 100 V > 1 kV Level 1 UL 94 V-0 @ 1.125 in 167
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
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Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout VINPP IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Differential Input Voltage VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Standard Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board v 3 sec @ 248C v 3 sec @ 260C SOIC-8 SOIC-8 SOIC-8 TSSOP-8 TSSOP-8 TSSOP-8 |D - D| Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VCC - VEE w 2.8 V VCC - VEE t 2.8 V VI v VCC VI w VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 25 50 2.8 |VCC - VEE| 0.5 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 265 265 Units V V V V mA mA V mA C C C/W C/W C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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Table 4. DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 4)
-40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current (Note 5) Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Min 10 1350 565 Typ 12 1450 725 Max 18 1550 870 Min 10 1400 630 25C Typ 12 1500 765 Max 18 1600 920 Min 10 1450 690 85C Typ 12 1550 825 Max 18 1650 970 Unit mA mV mV
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 10, 12) Vth VIH VIL Input Threshold Reference Voltage Range (Notes 2, 7) Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage 1125 Vth +75 VEE VCC -75 VCC Vth -75 1125 Vth +75 VEE VCC -75 VCC Vth -75 1125 Vth +75 VEE VCC -75 VCC Vth -75 mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13) VIHD VILD VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Cross-Point Voltage) (Note 3) Differential Input Voltage (VIHD - VILD) Input HIGH Current Input LOW Current D D D D -150 -150 1200 VEE 1163 VCC VCC -75 VCC -38 2500 50 10 -5 -30 150 150 -150 -150 1200 VEE 1163 VCC VCC -75 VCC -38 2500 50 10 -5 -30 150 150 -150 -150 1200 VEE 1163 VCC VCC -75 VCC -38 2500 50 10 -5 -30 150 150 mV mV mV
VID IIH IIL
75
75
75
mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Vth is applied to the complementary input when operating in single-ended mode. 3. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. 4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V. 5. All input and output pins left open. 6. All loading with 50 W to VCC - 2.0 V. 7. Do not use VBB as a reference voltage for single-ended PECL signals when operating device at VCC - VEE < 3.0 V.
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Table 5. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 10)
Symbol IEE VOH VOL Characteristic Negative Power Supply Current (Note 11) Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Min 10 2150 1365 -40C Typ 12 2250 1525 Max 18 2350 1670 Min 10 2200 1430 25C Typ 12 2300 1565 Max 18 2400 1720 Min 10 2250 1490 85C Typ 12 2350 1625 Max 18 2450 1770 Unit mA mV mV
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 10, 12) Vth VIH VIL VBB Input Threshold Reference Voltage Range (Note 8) Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage Output Voltage Reference 1125 Vth +75 VEE 1880 1980 VCC -75 VCC Vth -75 2070 1125 Vth +75 VEE 1880 1980 VCC -75 VCC Vth -75 2070 1125 Vth +75 VEE 1880 1980 VCC -75 VCC Vth -75 2070 mV mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13) VIHD VILD VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Cross-Point Voltage) (Note 9) Differential Input Voltage (VIHD - VILD) Input HIGH Current Input LOW Current D D D D -150 -150 1200 VEE 1163 VCC VCC -75 VCC -38 2500 50 10 -5 -30 150 150 -150 -150 1200 VEE 1163 VCC VCC -75 VCC -38 2500 50 10 -5 -30 150 150 -150 -150 1200 VEE 1163 VCC VCC -75 VCC -38 2500 50 10 -5 -30 150 150 mV mV mV
VID IIH IIL
75
75
75
mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Vth is applied to the complementary input when operating in single-ended mode. 9. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V. 11. All input and output pins left open. 12. All loading with 50 W to VCC - 2.0 V.
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Table 6. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.465 V to -2.375 V (Note 15)
Symbol IEE VOH VOL Characteristic Negative Power Supply Current (Note 17) Output HIGH Voltage (Note 16) Output LOW Voltage (Note 16) Min 10 -1150 -1935 -40C Typ 12 -1050 -1775 Max 18 -950 -1630 Min 10 -1100 -1870 25C Typ 12 -1000 -1735 Max 18 -900 -1580 Min 10 -1050 -1810 85C Typ 12 -950 -1675 Max 18 -850 -1530 Unit mA mV mV
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 10, 12) Vth VIH VIL VBB Input Threshold Reference Voltage Range (Note 8) Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage Output Voltage Reference VEE +1125 Vth +75 VEE -1420 -1320 VCC -75 VCC Vth -75 -1230 VEE +1125 Vth +75 VEE -1420 -1320 VCC -75 VCC Vth -75 -1230 VEE +1125 Vth +75 VEE -1420 -1320 VCC -75 VCC Vth -75 -1230 mV mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13) VIHD VILD VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Cross-Point Voltage) (Note 9) Differential Input Voltage (VIHD - VILD) Input HIGH Current Input LOW Current D D D D -150 -150 VEE+ 1200 VEE VEE+ 1163 75 50 10 -5 -30 VCC VCC -75 VCC -38 2500 150 150 -150 -150 VEE+ 1200 VEE VEE+ 1163 75 50 10 -5 -30 VCC VCC -75 VCC -38 2500 150 150 -150 -150 VEE+ 1200 VEE VEE+ 1163 75 50 10 -5 -30 VCC VCC -75 VCC -38 2500 150 150 mV mV mV
VID IIH IIL
mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Vth is applied to the complementary input when operating in single-ended mode. 14. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. 15. Input and output parameters vary 1:1 with VCC. 16. All loading with 50 W to VCC - 2.0 V. 17. All input and output pins left open.
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Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 18)
-40C Symbol VOUTPP Characteristic Output Voltage Amplitude (See Figures 2 & 3) tPLH, tPHL tSKEW tJITTER fin < 3 GHz fin < 6 GHz 500 270 80 700 350 130 3 30 0.2 2 75 30 700 70 180 25 60 1 12 2500 120 75 30 500 270 80 700 350 130 3 30 0.2 2 700 70 180 25 60 1 12 2500 120 75 30 500 270 85 700 300 135 3 30 0.2 2 700 70 185 25 60 1 12 2500 120 mV ps ps ps ps Min Typ Max Min 25C Typ Max Min 85C Typ Max Unit mV
Propagation Delay to Output Differential @ 1 GHz Duty Cycle Skew (Note 19) Device-to-Device Skew RMS Random Clock Jitter (Note 20) fin < 6 GHz Peak-to-Peak Data Dependent JItter (Note 21) fin < 6 Gb/s Input Voltage Swing / Sensitivity (Differential Configuration) (Note 22) Output Rise/Fall Times (20% - 80%) Q, Q
VINPP tr tf
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 18. Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50 W to VCC. Input edge rates 40 ps (20% - 80%). 19. See Figure 9 tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical transitions and conditions @ 1 GHz. 20. Additive RMS jitter with 50% duty cycle clock signal at 6 GHz. 21. Additive Peak-to-Peak data dependent jitter with NRZ PRBS 223-1 data rate at 6 Gb/s. 22. VINPP(max) cannot exceed VCC - VEE. (Applicable only when VCC - VEE < 2500 mV). Input voltage swing is a single-ended measurement operating in the differential mode. 0.8 OUTPUT VOLTAGE AMPLITUDE (V) 0.7 0.6 0.5 25C 0.4 0.3 0.2 0.1 0.0 1 2 3 4 5 6 7 8 INPUT CLOCK FREQUENCY (GHz) 85C -40C OUTPUT VOLTAGE AMPLITUDE (V) 0.8 0.7 -40C 0.6 0.5 0.4 0.3 85C 0.2 0.1 0.0 1 2 3 4 5 6 7 8 INPUT CLOCK FREQUENCY (GHz) 25C
Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) and Temperature at VCC - VEE = 3.3 V
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) and Temperature at VCC - VEE = 2.5 V
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OUTPUT VOLTAGE AMPLITUDE (100 mV/div) OUTPUT VOLTAGE AMPLITUDE (100 mV/div) TIME (62 ps/div)
TIME (32 ps/div)
Figure 4. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 (Total System Pk-Pk Jitter is 16 ps. Device Pk-Pk Jitter Contribution is 3 ps)
NOTE:
Figure 5. Typical Output Waveform at 6.125 Gb/s with PRBS 223-1 (Total System Pk-Pk Jitter is 17 ps. Device Pk-Pk Jitter Contribution is 4 ps)
VCC - VEE = 3.3 V; VIN = 700 mV; TA = 25C.
190 PROPAGATION DELAYS (ps) 180 170 160 150 140 130 120 110 100 90 80 2.375 2.5 3.3 POWER SUPPLY VOLTAGE (V) 3.465 -40C 85C 25C RISE/FALL TIME (ps)
120 110 100 90 80 70 60 50 40 30 2.375 2.5 3.3 POWER SUPPLY VOLTAGE (V) 3.465 -40C 25C 85C
Figure 6. Propagation Delay versus Power Supply Voltage and Temperature
18 17 IEE CURRENT (mA) 16 15 14 13 12 11 10 -40 25 VCC - VEE = -2.375 V
Figure 7. Rise/Fall Time versus Power Supply Voltage and Temperature
VCC - VEE = -3.465 V
85
TEMPERATURE (C)
Figure 8. IEE Current versus Temperature and Power Supply Voltage
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D D Q Q tPLH VINPP(D) = VIH(D) - VIL(D) VINPP(D) = VIH(D) - VIL(D)
VOUTPP(Q) = VOH(Q) - VOL(Q) VOUTPP(Q) = VOH(Q) - VOL(Q) tPHL
Figure 9. AC Reference Measurement
Vth
D
D
D Vth
D
Figure 10. Differential Input Driven Single-Ended
Figure 11. Differential Inputs Driven Differentially
VCC Vthmax
VIHmax VILmax
VCC VCMmax
VIHDmax VILDmax VID = VIHD - VILD VIHDtyp VILDtyp
Vth
VIHTYP VthTYP VILTYP VIHmin VILmin
VCMR
Vthmin GND
VCMmax GND
VIHDmin VILDmin
Figure 12. Vth Diagram
Figure 13. VCMR Diagram
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 14. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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ORDERING INFORMATION
Device NB6L16D NB6L16DG NB6L16DR2 NB6L16DR2G NB6L16DT NB6L16DTG NB6L16DTR2 NB6L16DTR2G Package SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) TSSOP-8 TSSOP-8 (Pb-Free) TSSOP-8 TSSOP-8 (Pb-Free) Shipping 98 Units / Rail 98 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 100 Units / Rail 100 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AH
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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PACKAGE DIMENSIONS
TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8
5
L
1 PIN 1 IDENT 4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
-W- G DETAIL E
DIM A B C D F G K L M
ECLinPS is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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